1. Field of the Invention
The present invention relates to preparing a buried LOCOS collar in a trench DRAM by using an integration scheme that: avoids widening of the trench CD (critical dimensions); avoids the presence of a thick collar inside the trench that reduces the available diameter of the trench for trench processing and trench fill; and improves the resistance of an oxide collar to dopant diffusion during gas phase doping.
2. Description of the Prior Art
In the field of making electronic devices, current objectives focus on fitting significantly more active devices in a specific area of a semiconductor substrate. In this effort, reduction of the minimum geometries of the semiconductor device entails a reduction in the spacing between adjacent semiconductor devices, as this aids in increasing the density of the active surface area of a semiconductor substrate. For example, when semiconductor devices are positioned too close to one another on a substrate, parasitic currents and capacitances result that degrade the performance of the circuit. Accordingly, significant effort is focused into designing methods and structures to electrically isolate adjacent semiconductor devices while at the same time permitting the semiconductor devices to be positioned close to one another.
Amongst the isolation techniques used in the past is the local oxidation of silicon (LOCOS) technique. The LOCOS structure resulting from this technique is one where the surface of the active semiconductor is oxidized between the active regions of the semiconductor surface to alleviate electrical interaction between adjacent devices. Nevertheless, the effectiveness of the LOCOS method degrades as the devices become closer due to the fact that parasitic currents develop between adjacent devices beneath the LOCOS structures. These currents are sometimes referred to as xe2x80x9cpunch-throughxe2x80x9d currents because they travel through the bulk semiconductor underneath the LOCOS structures.
A further method of isolation of adjacent structures in a semiconductor device is the use of TI (Trench Isolation). In this method, trenches are etched between adjacent active regions of the semiconductor substrate. The deep trenches are effective means of preventing the so called xe2x80x9cpunch-throughxe2x80x9d currents. Nevertheless, in placing these trenches in semiconductor devices, leakage problems tend to arise in the devices themselves. That is to say, if the trench is used to isolate a FET (Field Effect Transistor), the performance of the transistor can be degraded due to creation of a conduction path across the channel of the transistor along the trench sidewall. The current path results from leakage along the surface of the trench sidewall. Therefore, although the trench can eliminate the xe2x80x9cpunch-throughxe2x80x9d current between adjacent devices, the trench may also degrade performance of the device that it is intended to isolate.
U.S. Pat. No. 6,136,633 discloses a method of forming an improved buried contact junction. The method entails:
providing a gate oxide layer over the surface of a semiconductor substrate;
depositing a first polysilicon layer over the gate oxide layer;
forming a photoresist mask over the first polysilicon layer having an opening over the planned buried contact;
etching the first polysilicon layer not covered by the photoresist mask;
cutting away a portion of the photoresist mask at the edges of the opening to expose a portion of the first polysilicon layer at the edges;
etching the gate oxide layer not covered by the mask wherein the etching has a reduced selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening;
implanting ions through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact;
removing the photoresist mask; and
depositing a second polysilicon layer overlying the first polysilicon layer and the buried contact to complete the formation of the buried contact in the fabrication of the integrated circuit device.
A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM is disclosed in U.S. Pat. No. 5,827,765. The electrical connection is formed by selectively controlled outdiffusion of a N-type or P-type dopant present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. The epitaxially grown single crystalline layer functions as a barrier to excessive dopant outdiffusion that occurs in the processing of conventional DRAMs.
U.S. Pat. No. 6,090,686 discloses a LOCOS isolation process using a layered pad nitride and dry field oxidation stack, as well as a semiconductor device employing the same. The method of manufacturing the isolation structure comprises:
depositing a first isolation stack-nitride sublayer over a substrate at a first deposition rate;
depositing a second isolation stack-nitride sublayer over the first isolation stack-nitride sublayer at a second deposition rate that is different from the first deposition rate; and
depositing a third isolation stack-nitride sublayer over the second isolation stack-nitride sublayer at a third deposition rate that is subsequently equal to the first deposition rate.
U.S. Pat. No. 5,350,941 discloses a trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench. The isolation structure comprises:
a LOCOS structure formed on the outer surface, the LOCOS structure comprising a first bird""s beak structure disposed laterally adjacent the first active region and a second bird""s beak structure disposed laterally adjacent the second active region;
a trench plug disposed in a trench formed through the LOCOS structure between the first and second bird""s beak structures and in the semiconductor layer, the trench comprising sidewalls defining an interface between the trench plug and the semiconductor layer; and a channel stop region located in the sidewalls of the trench.
A schematic design of a conventional vertical DRAM capacitor cell after processing the deep trench (DT) etch, buried plate, bottle and collar, resembles that shown in FIG. 1.
In this structure of FIG. 1, there is shown a pad nitride 10, isolation collar 11, contact 12, buried plate 13, and a storage capacitor 14. It can be seen from this figure that there is a reduction of trench diameter after the collar formation in this conventional collar formation scheme.
There is need in the art of preparing buried LOCOS collars in trench DRAMs to provide an integration scheme that: avoids LOCOS oxidation consumption of silicon from the trench side walls; avoids widening of the trench CD (critical dimensions); avoids the presence of a thick collar inside the trench that reduces the available diameter of the trench for trench processing and trench fill; and improves the resistance of the oxide collar to dopant diffusion during gas phase doping.
One object of the present invention is to provide a process for making a buried LOCOS collar in trench DRAMs that avoids the widening of the trench at the height of the buried strap.
Another object of the present invention is to provide a process for incorporating a buried LOCOS collar in trench DRAMs that avoids the widening of the trench at the height of the buried strap and thereby allows extension of the technology to small groundrules.
A further object of the present invention is to provide a process flow for incorporating a buried LOCOS collar in trench DRAMs that avoids widening of the trench at the height of the buried strap, thereby permitting extension of the technology to small groundrules, as well as avoiding reduction of free trench diameter by virtue of the fact that the collar is placed outside the trench.
A yet further object of the present invention is to provide a process flow for a buried LOCOS collar in trench DRAMs that avoids the presence of a thick collar inside the trench that reduces the available diameter of the trench for trench processing and trench fill.
A still further object of the present invention is to provide a process flow for incorporating a buried LOCOS collar in trench DRAMs that does not suffer from the small resistance of an oxide collar to dopant diffusion during gas phase doping.
In general, using the process flow scheme of preparing a buried LOCOS collar in trench DRAMs of the present invention provides a process and collar characterized by the following advantages:
fabrication of the collar after DT (Deep Trench) etch prior to trench processing;
self-aligned bottle and gas phase doping;
no consumption of silicon at the depth of the buried strap;
no reduction of trench diameter;
a nitride layer to protect trench sidewalls during gas phase doping; and
no thermal budget for collar formation after node deposition is needed.